Gate level Simulation passes but design fails on target borad

Okay, For the timing issue:

Type : Slow Model Clock Setup:

Slack : -7.425 ns

Required Time : 40.00 MHz ( period = 25.000 ns )

Actual Time : 30.84 MHz ( period = 32.425 ns )

From : "...input path to input of the filter"

To : "...output path to output of the filter"

From Clock : path to 40MHZ clock from PLL

To Clock : path to 40MHZ clock from PLL

Failed Paths: 7874

40MHZ is input clock to a different module to generate 500 KHZ enable or ready signal. I use this ready or enable signal which is 500KHZ as clock for my filter. i dont use 40MHZ directly even once.

I added this path in assignment editor, with assignment name "clock enable multicycle" and a value = 2. But error is still present.

Perhaps, i should have assigned "Multicycle" and a value of 2.

I am compiling the project and will update you soon.

Please suggest, how to proceed.