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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Hello kaz,

I requested a friend of mine to plot the response for the filter.

Please find the attached picture which looks correct.

>> a = [1.000000000000000, -1.999747125328010, 0.999748704265674];

>> b = [ 0.999886916919553, -1.999747125328010, 0.999861787346121];

fvtool(b,a)

It looks like 100 Hz 20 dB.

Please have a look and advice.