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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I had another doubt, is it a big concern and may be a reason for failing on board??

2)

I see that fast/slow model results in timing analyses show failures linked to my design. It indicated a different (40MHz) clock domain in the from/to section of the report. 40MHz is used for other sections and I don't use 40 Mhz for this piece of design.

Please advice.