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Altera_Forum
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14 years ago

Gate level Simulation passes but design fails on target borad

Hello, I am implementing a filter (2nd order) in Quartus Stratix II device running at 500KHz. I simulated the design using ModelSim. My Target hardware consists of stratix II device. Input...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks. Great. But it should attenuate at 100 Hz till -10 dB, i believe.

Fs = 500 KHz in my case.

I forgot to mention it.

To convert the folating numbers to decimal, I need to decide on the bits size. For 30 bits => (float value)*2^30 => results in coefficients that i have mentioned.

It is okay in Gate level simulation, but fails on board.

Please advice.