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Altera_Forum's avatar
Altera_Forum
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16 years ago

Gate level sim - EDA netlist writer won't run

I'm trying to run gate level simulation in modelsim on my design, but the EDA netlist writer will not run! If I simply start "EDA Gate Level Simulation" then "Analysis & Synthesis" is run (succ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Aaaaaaaaaah, you can run "Compile Design"...

Why the same results wouldn't be achievable running them one by one is beyond me.....................................................................................

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Hi,

you need a full compile for the gatelevel simulation, because the simulation includes the timing. The timing information is available after the design is P&R und the timing is analyzed.

Kind regards

GPK