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Altera_Forum
Honored Contributor
Honored Contributorgate lev sim not working as expected
hello everybody im quite new in developing for FPGA. I have started wih DE0-nano board. im learning just programming an easy FSM that performs elementary operations. i have followed the tut...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Sorry for the ignorance, For test bench code you mean eda netlist file in verilog generated for modelsim? --- Quote End --- No - the testbench is the code you use to test your code - you have to generate inputs for the design somehow...
