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Altera_Forum's avatar
Altera_Forum
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9 years ago

gate lev sim not working as expected

hello everybody im quite new in developing for FPGA. I have started wih DE0-nano board. im learning just programming an easy FSM that performs elementary operations. i have followed the tut...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Sorry for the ignorance,

For test bench code you mean eda netlist file in verilog generated for modelsim?

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No - the testbench is the code you use to test your code - you have to generate inputs for the design somehow...