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Altera_Forum
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9 years ago

gate lev sim not working as expected

hello everybody im quite new in developing for FPGA. I have started wih DE0-nano board. im learning just programming an easy FSM that performs elementary operations. i have followed the tut...
Altera_Forum's avatar
Altera_Forum
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9 years ago

In an asynchronous process, all signals must be assigned in all cases, otherwise latchea will be created.

For example, when current state is 01, next state is only assigned when the counter gets to 7, otherwise it holds its state. This creates a latch. You must at least assign it to current state to avoid the latch.

The same for finito. It is only assigned here. This creates a latch.