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Altera_Forum
Honored Contributor
Honored Contributorgate lev sim not working as expected
hello everybody im quite new in developing for FPGA. I have started wih DE0-nano board. im learning just programming an easy FSM that performs elementary operations. i have followed the tut...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I Notice the next_state and finito signal is not assigned in all branches, so it will create latches. This might be what is causing the problems. --- Quote End --- what do you mean for .. is not assigned in all branches?
