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Altera_Forum
Honored Contributor
Honored Contributorgate lev sim not working as expected
hello everybody im quite new in developing for FPGA. I have started wih DE0-nano board. im learning just programming an easy FSM that performs elementary operations. i have followed the tut...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- That is not a testbench - that ios the waveform output from the design. What code are you using to test your design? --- Quote End --- synthesis code is VHDL ModelSim code is converted in Verilog
