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16 years agosrf6791 (http://www.alteraforum.com/forum/member.php?u=11003):
Thanks for your answer. I checked my design with your guideline 1 , and I found a problem: the posedge of clk near the change edge of the address of the ROM , so I add an inverter between the clk to the ROM , OK , the data became correct. Thank you again~