Fully parallel architecture of LDPC decoder

I am currently working on LDPC decoder of fully parallel architecture and platform is verilog.I refer some of the pdf like R.G.Galleger LDPC thesis report as well as some other thesis report like "MSc_thesis_ draft_sept_20_2010" LDPC and also google around a bit.Till now i have implemented the functional unit part and the controller part as specified in that Msc thesis report.Now i am stuck with the rest of the design as i am not getting a proper solution neither i dont know that the architecture is for a fully parallel one.So anyone if has any related pdf about the architecture of fully parallel or can help me in my designing part....please tell me what to do.