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Altera_Forum's avatar
Altera_Forum
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8 years ago

Full compulation for large IO pins

Hi I would like to perform full compilation for component (not the Top Level) that has large IO pins. Im looking at over thousands bits in output bits. But I need to know the total LEs and Fmax...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Possibly, I have no idea how you've implemented the design (and I have no experience with encryption algorithms)

If it's currently some large amount of interdependent logic, the pipelines could reduce the interdependence per clock cycle (and hence reduce routing requirement)

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Alright! thanks for the advice. I shall explore further on this!