FSM behaving strangely

The code posted should be cleaned up a bit...

<as posted>

BEGIN

PROCESS(clock)

BEGIN

IF Reset = '1' THEN

state<=A;

PC<="0000000000000000";

ELSIF(clock'EVENT AND clock='1') THEN

<should be>

BEGIN

PROCESS(clock, reset)

BEGIN

IF Reset = '1' THEN

state<=A;

PC<="0000000000000000";

readinstructionmemory <= '0';

readregs <= '0';

writeregs <= '0';

performadd <= '0';

performmultiply <= '0';

readdatamemory <= '0';

writedatamemory <= '0';

ELSIF(clock'EVENT AND clock='1') THEN

Also, the simulation should have a reset condition(set reset to '1' for a couple clocks and then drop it low, assuming thats what will actually happen). It's good practice to init all outputs/buffers and signals with the reset to ensure predictability.