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Altera_Forum's avatar
Altera_Forum
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18 years ago

FSM behaving strangely

I have a simple set of VHDL code that steps through an FSM doing certain things. It compiles fine and I can design my test waveform. However when I run the simulation some of the pins don't show up...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

I don't get 'X' in output when simulating your design, even when omitting the reset as you did. Could be due to different device family, Quartus version or global synthesis options. However, with correct reset, no 'X' should be seen, unconditionally.

Regards,

Frank