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Altera_Forum's avatar
Altera_Forum
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8 years ago

FSM: a state gets latched

Hi,

i am running a state machine.

Simulation shows everything is OK.

Real life implementation is showing otherwise.

I keep track of the states using on board LEDS showing the current FSM state.

The problem is that at a certain point (couldn't figure out if there is a specific sequence except that its not from the WAIT STATE), the FSM transfer to the INIT STATE and gets stuck there until i do a POWER reset, which is weird by itself because there is no such transition possible, as i made sure that the reset_L signal is not LOW.

and gets stuck at that state, even though that even if such a transfer should happen, an immediate transfer to WAIT state should happen but doesn't.

I cant find the reason and the solution, please help...

THE CODE IS ATTACHED

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    I returned to the one hot style, bacause i wanted to get to the bottom of things.

    The problem were the asynchronous signals.

    I buffered the through a couple of FF, now all seem OK.

    Thanks everyone, you helped me a lot.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Reducing logic a bit, you see that many FSM transition conditions include TRIG[0] as direct input, e.g. 

    case (state)				
WAIT: 																	
	if (TRIG & !trig_SI_old)													
		state <= WAIT_2_X;											
WAIT_2_X: 														
	if(!TRIG)															
		state <= WAIT;

    Each of this conditions involves a data path to two state FFs, one to be set and one to be reset if the condition occurs. Flipping TRIG[0] in coincidence with the active clock edge (during the forbidden setup and hold window) can cause either both FFs set or both FFs reset, depending on clock skew and logic delays. The latter case has a good chance to act as illegal stuck state.

    Adding synchronizer FFs for TRIG[0] makes all state FFs see a consistent input condition. Safe state machine encoding causes detection of any illegal state and reset to INIT.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    So the FPGA is "alive" and keeps working, but the state machine, for whatever reason, is being thrown to INIT, and latches there.