FSK Modulation in VHDL

Yes, but when I tried to constrain the counter still I am having the error. I will explain how the code works, maybe you will have an idea about it.

First of all, the clk_cycles_s is used to push each values of fsk_data_i, fsk_u_i and fsk_l_i after every 1023rd clock cycle because that's the main motive of my design. I am designing a PLL that needs to be clocked only after every 1023rd clock cycle. After the first 1023rd cycle(assume), new values of fsk_data_i, fsk_u_i and fsk_l_i has to be provided as per my code(sorry i didn't declare in my testbench, but checked only for a single values of all the above three, its working properly). Once all the 22 bits of fsk_data_i (since i have defined the bit width as 22), new values for fsk_data_i, fsk_u_i, fsk_l_i should be defined, which I don't know how to do.

What I need exactly is, I need to change the inputs when all the 22 bits of the fsk_data_i are checked. I think so , you have understood the manner in which my code actually works. I need to help me to solve this issue