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Altera_Forum's avatar
Altera_Forum
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11 years ago

Frequency variation in Quartus II with block diagram programming

Hi guys, I am facing problem in varying frequency of a square wave signal in block diagram way of programming. Find the schematic of the block diagram in the Attachment. Pls suggest ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

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Did you review the blurred picture in your post? How can you expect an answer referring to it?

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I will explain the logic which is given in the picture.

Actually I need to generate a square wave output (0 - 10) volts in Block diagram programming. The schematic of the description is as below:

1) The Internal clock is used to generate the Ramp signal.

2) The Ramp is compared with a constant to generate square wave signal.

3) Pin settings are done for 11 outputs of the DAC.

My Cyclone II Altera chip (EP2C70F672C8) has Internal clock frequency of (400 MHz) which is able to produce a square wave output of (12 kHz) max. But I need (40 kHz) square wave signal.

Pls provide with your suggestions for the above problem.