Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

FPGA symbol creation

Dear all,

I would like to know whether FPGA symbol can be created using mentor graphics design capture s/w and Quartus 8.1 Quartus has generated a EDA netlist file. It is stated that modelsim i/o designer s/w is needed for FPGA symbol creation. But i don't have a licensed version. Will the evaluation version be sufficient for symbol creation? Can the symbol be created using design capture s/w also. Please suggest me.

Thanks & regards

praveen

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Yes, it can be done.

    I have a clunky home-brewed bit of C which will generate DC/DV symbols from a text file which can reasonably easily be hacked from Altera's pin list.

    It produces a text file output that ASCII-IN can import into a DC/DV library.

    IO designer is quite nice, but comes with a fairly hefty price tag.