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Altera_Forum's avatar
Altera_Forum
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17 years ago

FPGA symbol creation

Dear all, I would like to know whether FPGA symbol can be created using mentor graphics design capture s/w and Quartus 8.1 Quartus has generated a EDA netlist file. It is stated that mode...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Yes, it can be done.

I have a clunky home-brewed bit of C which will generate DC/DV symbols from a text file which can reasonably easily be hacked from Altera's pin list.

It produces a text file output that ASCII-IN can import into a DC/DV library.

IO designer is quite nice, but comes with a fairly hefty price tag.