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Altera_Forum
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11 years ago

FPGA setup / hold times

In order to constrain I/O timing I need the setup and hold times of the device I am interfacing with. Usually that can be found in the data sheet of that chip. But what if I am interfacing wi...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Thanks kaz and Rysc.

I like both approaches.

kaz's is basically straight forward and done as if FPGA 2 was some third party chip where you can look up the timing requirements in the "data sheet".

Of course if the FPGA 2 design is recompiled you have to check the "data sheet" report again every time to see if it has changed, just like with a third party chip that has changed.

Rysc's approach avoids that by giving FPGA 2 a requirement and therefore let TimeQuest warn you if it doesn't meet it anymore after a recompile.

The theoretical disadvantage here is that FPGA 2 might end up with more slack than necessary after a recompile and make it harder for FPGA 1 to reach timing.