FPGA setup / hold times

You can do a min in a similar manner. In this example there isn't much need for one, as the hold relationship is 0ns across the interface, which is pretty much impossible(a huge amount of clock skew on the receiver might make it possible).

After the compile of fpga1 where the set_output_delay was 20, you may see in the fast timing model that it's Min Tco is 3ns. Then go ahead and put a

set_output_delay -clock virt_clk -min -3.0 [get_ports fpga1_dout*]

(Add the -max option to the other constraints, I forgot to do that). This says the min external delay is -3ns, so FPGA1 must get it's data out more than +3ns after the clock to meet hold timing. Actually, let'ss loosen the constraint a bit to something like -2ns.

Now for fpga2, you know fpga1 has a min output delay of 2ns, and the board delay is 1ns, so do:

set_input_delay -min -clock virt_clk 3.0 [get_ports fpga2_din*]