Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- I see, so much to learn.. Got sidetracked in learning VHDL for a bit, but the SignalTap looks promising :D --- Quote End --- Just so you understand, signaltap is meant as a debug tool, not a verification tool. Verification should be done as much as possible in simulation. If you are designing with the intention to use signaltap, you need to re-assess your design goals.