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chris_notsch's avatar
chris_notsch
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5 years ago

Forcibly specify correct toggle rate for LVDS pin

Dear Community, We are facing a critical issue in implementing a design using a Cyclone 10 LP with a pwm generator logic driving a LVDS pin. The resolution of the output logic is 1ns (1 Ghz delay...
JonWay_altera's avatar
JonWay_altera
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5 years ago

Hi Chris,

Could you attach a simplified design that shows the error?

chris_notsch's avatar
chris_notsch
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5 years ago

@JonWay_C_Intel I have created and attached two configurations of a example project configured to run on the Intel Cyclone 10 LP Evaluation Kit.

one configuration showing the error message, and one showing that the settings rejected by quartus are valid (using on the fly reconfiguration to allow compliation with lower clock speed).

The example contains a description on how it is constructed and how to connect it as well as the resulting output waveforms.

Materials required:

EK-10CL025U256

Oscilloscope with >= 1Ghz bandwith & differential probe, 100 Ohm LVDS termination resistor, + 1 Single ended probe

Quartus Prime 20.1.0 Build 771 06/05/2020 SJ Lite Edition

Thank you for your support,

Chris