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2. Not quite sure what exactly you're trying to do. In An FPGA, you cannot connect multiple signals together - the hardware doesnt allow it. The only place it is possible is the IO tristates, and it is only possible to drive an internal signal against an external one. You'll need to do multiple assigns to get the tri states working:
assign io = (enable) ? a : 1'bz;
assign a = (~enable) ? io : 1'bz;
Of course, you would only use one of the above in the chip. The other would be in a testbench.
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1. The chip (I am testing MAX V) can only be programmed from blaster and I never tested JTAG on that. Although JTAG is listed in handbook, the dev board has a J14 for JTAG, but the TDO and TMS are unconnected so JTAG cannot be used. As an off-topic question: does Stratix have JTAG debugging interface? And is it possible to read/write certain registers in runtime with that? Does doing that require huge amount of work because of the parallel/sync/timing issue of the circuit, comparing to JTAG debugging on off-the-shelf chips? If such per-register JTAG access were to be done, upon receiving each valid incoming JTAG signal the CPLD/FPGA would need to halt the entire chip (closing many paths/clocks, etc.) , require much complicated circuitry and that would also introduce significant delay / speed downgrade to the chip. I wonder if that had ever be implemented.
2. "The other would be in a testbench". Do you mean the real "ee engineer's testbench (
http://www.customtestbenches.com/images/electrical-test-bench-lg.jpg)" rather than the virtual HDL workbench? And that we manually connect a driven wire (with opposite value to the IO output) to the IO output, and use scope to test the contended "X" value?
3. The "io" and "a" are related by "enable", but it didn't seem clear whether they are tristate or metastable. Could you explain in detail how they produce an contented "X"?
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That's just how verilog designed... VHDL on the other hand... multiple drives
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4. I saw you and Pieter in another thread (
http://pietervanderstar) all used VHDL example, and you referred to an limitation of verilog in this one. Does Altera or IC professionals consider verilog incomplete and amateurish, some how like C++ programmers viewing javascript?
greg
Honored Contributor
