New Contributor
Occasional ContributorI happen to have a design in Quartus Prime Lite 20.1 that has a PLL with multiple outputs, but only one is actually used in the design.
I could see one of the unused clock outputs in Signal Tap node finder and select it; add a signal to monitor and recompile. I haven't seen any complain by Quartus, so I assume your case should be working too.
I cannot test this on an actual board though, but at least I can see that an unconnected PLL output can be selected in Signal Tap.
Could you parse the Quartus (critical) warnings for anything related to this clock when it is not connected to anything (other than Signal Tap)? Even if it doesn't seem much?
As for the problem of the inverted signal, I don't know much more. I suppose the write_strobe signal is not connected to a differential pair and you are not monitoring two different poles? (Sorry if the question is dumb, but I have found Signal Tap to be reliable in my use cases).
Good luck
New ContributorHi MathiasB,
thanks for your suggestions.
I resolved the issue with the inverted signal thanks for your suggestions. I used the "pre-synthesis" filter in SignalTap's node selector and tapped the signal inside a "component" rather than in the top-entity where it is generated. This subsequently displayed it the right way up (see my reply to sstrell...).
I will do as you suggest and look for references in the Quartus (critical) warnings.
No question is dumb and thank you for asking them, a friend of mine's Dad used to say "the only dumb question is the one you don't ask", I appreciate your input.
regards
PhilipJ
