Force Quartus to keep a signal for SignalTap to use

Hi, replying to all of you who have been kind enough to respond:

I have tried the suggested options and none of them seem to work.

To be clear I am using Quartus Prime Lite so is it likely that these options may be "crippled" in this free version?

To give an example:

I am working with serial bit streams that consist of LRCLK (96kHz square wave), an SCLK (256 * LRCLK) and a serial stream of data bits at SCLK frequency (some may recognise this as a TDM8 digital audio stream).

SCLK is the highest frequency I have in the design (24.576 MHz) so to capture the signals in SignalTap I use a 4* PLL to give me a Global 98.304 MHz clock, SignalTap is the only part of the design that uses this Global clock.

After compiling; this clock is not presented as an available node for SignalTap's clock configuration, I have tried every one of the available filters in the Node Selector but there's nothing.

If I go back to the VHDL code and connect Global_98 to a device pin and then re-compile, the node is now available and I can select it in SignalTap.

HOWEVER; if I then go back to the VHDL code and delete Global_98's connection to a pin then after compilation SignalTap now shows Global_192 in red text which I take to mean this node has been optimized out! (even though SignalTap is using it) and if I try to capture data with SignalTap is says "waiting for clock".

This is not the only case where nodes are removed by optimization but it is probably the most frustrating.

As I mentioned, I have been "working around" this behaviour by applying signals to device pins to force them to remain but I don't understand why my extensive use of "keep" "preserve" and "noprune" don't achieve what I expect of them.

Thanks for you replies and interest in my problem

regards

PhilipJ