Force a reg not to use M9K but logic

Hi

I do use M9K for ROM tables and this works fine

I also have to use quite some latches since I works as pipeline

The problem are when I do use latches then QuartusII on some of the latches do use M9K and other a logic , then I do not have enough M9K for ROM

I have tried different combination with ramstyle="logic" in my verilog

(* ramstyle = "logic" *) reg [63:0] Block_out;

reg [63:0] Block_out /* synthesis ramstyle = "logic" */;

And still some of my reg do use M9K

Any hint?