Altera_Forum
Honored Contributor
Honored ContributorFor loop
hello
I want to check an array. which one is quicker? using for loop or using a counter that counts up at the "posedge" of the clock. thanksForum Discussion
11 Replies
Altera_ForumYour posts here indicate a fundamental misunderstanding about what Verilog HDL is. When you use Verilog to program an FPGA the Verilog code is not at all like a software language such as C or Basic. Instead, the Verilog code describes a hardware system composed of flip-flops, logic gates, etc. It does not tell the FPGA to execute Verilog statements. The FPGA is not a microprocessor that executes lines of code sequentially.
- Altera_Forum
yes I agree with you.
but I think you didnt get my point. I meant if I program a FPGA with these two programs which one would be quicker? because my program should be running in real-time so it should be as fast as it can. In other words which style is quicker? for loop or counter - Altera_Forum
again - you dont seem to understand the nature of digital logic. In digital logic there is no "array", just some form of memory. If you build it out of registers you could access all array elements in parallel. If you had a physical memory you could only access the elements sequentially.
But it all depends on the context and what you're trying to do. - Altera_Forum
Let's go back to your original ambiguous post.
--- Quote Start --- I want to check an array. --- Quote End --- Check it for what? I'm going to assume you mean you want to examine each element of the array and compare it with another value to see if that value matches any elements. --- Quote Start --- which one is quicker? --- Quote End --- Quicker in terms of what? Shortest propagation delay within one clock cycle? or least number of clocks cycles with the shortest clock period? Or maybe something else. --- Quote Start --- using for loop or using a counter that counts up at the "posedge" of the clock. --- Quote End --- A for loop is a programming concept - it does not exist on an FPGA. When you synthesize it, the loop get unrolled into parallel hardware blocks, and it all depends on what is inside the for loop to know how that affects the timing. - Altera_Forum
compare these two codes:
1)for(i=0;i<1024;i=i+1) if(array==1)array=0; 2)case(ps) ... 1:begin if(counter==1024) ns=2; else begin ns=1; if(array[counter]==1) array[i]=0; count=1; end end ... always@(posedge clk) if(count==1) counter=counter+1; which one is running faster? if they have same clock. you know what I want to know?! I want to know which style is better generally.
- Altera_Forum
think in terms of hardware.
The first option is trying to search an array in a single clock cycle. This would be impossible/impractiacle in a real circuit. the 2nd option is more realistic, but will take n clocks to search the array, depending on how big the array is. You are clearly not thinking in terms of hardware. Stop thinking this is like software. - Altera_Forum
The first style requires the array to be implemented in logic elements. For an array size of 1024, this would be at least "impracticable", as mentioned by Tricky.
To implement an array in internal block RAM, the array elements must be accessed sequentially, but additional conditions must be met to allow RAM inference from the code. I doubt that the style 2) example will work as is, but somethinking of this kind should. The example reads and writes different array elements simultaneously, which refers to a dual port RAM. You should review the Altera RAM inference templates for the suggested syntax. - Altera_Forum
OK. I got it. thank everyone.
but is it always impossible to search a part of an array in single cycle? - Altera_Forum
if your array is parallel bus then you can check all its components in one cycle
- Altera_Forum
By the way, is your array an array of single bits, or are there other values besides 1 and 0? You didn't show the declaration of array, that could make a big difference in how you go about implementing it.
