For Loop Complexity

Cause a HDL iteration scheme is completely executed at compile time and the resulting logic handed over to the usual optimizing process, the resource utilization doesn't depend on the particular coding style, as long as the logic function is unchanged.

To estimate the possible complexity, you should consider meaningful examples. your below example isn't, cause the same expression is added 652 times (x an y are constant during iteration).

for(k=0;k<652;k=k+1)
begin
F=F+(u*v);
end

The synthesis problem with this particular example isn't the iteration, but the indexing. It forces inference of multiplexers. Depending on the x/y range and u/v bit size, it may already go beyond the logic cell and routing resources of a medium size FPGA. With x and y varying during the iteration, it's most likely unsynthesizable.

I assume, that the code has been written by someone, who didn't yet understand the meaning of iteration schemes in HDL.