For Loop Complexity

Let me explain my view and experience with for loops. discussion relates to vhdl and I hope it applies to verilog or other HDL.

when you declare for loop then you are asking the compiler to insert the statements for you(to unroll sequentially). The compiler will do that at compile time and the hardware got nothing to do with the loop from that point on.

for example

for i in 0 to 7 loop

a(i) <= '1';

end loop;

the compiler will unroll the loop into:

a(0) <= '1';

a(1) <= '1';

....

a(7) <= '1';

thats all, thus if instead say:

for i in 0 to 7 loop

a <= '1';

end loop;

the compiler will unroll the loop into:

a <= '1';

a <= '1';

....

a <= '1';

which is meaningless and only last assignment is taken to hardware.