New Contributor
Regular ContributorHi,
As I understand it, you have some inquries related to CV floating IP. Sorry as I am not clear with the FIFO buffer that you are referring to. For your information, you may refer to the Floating-Point IP Cores User Guide (https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altfp_mfug.pdf) for the supported floating point IPs in CV device to see if any of them suit your target application. Note that I am unable to locate any specific FIFO buffer keyword in the user guide.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorHi Chee Pin,
Thank you so much for your reply. Yes, as you've mentioned there wasn't any ip mentioned on the user guide, so I guess there is no ip for it. But I tried running the the following code to build a buffer, and there were no errors that came up. But, when I give in values on the test bench and simulate through Modelsim, it gets rounded to the closest integer. Is there anything wrong with my code or is there any advice that I could use, to display a floating-point number instead of the closest integer value?
`define BUF_WIDTH 3
`define BUF_SIZE ( 1<<`BUF_WIDTH )
module FifoBuffer2( clk, reset, in_x, out_x, write, read, emp, full);
input reset, clk, write, read;
input [8:0] in_x;
output [8:0] out_x;
output emp, full;
reg[8:0] out_x;
reg emp, full;
reg[`BUF_WIDTH -1:0] rd_ptr, wr_ptr;
reg[8:0] buf_mem[`BUF_SIZE -1 : 0];
always @(posedge clk)
begin
if( write && !full )
buf_mem[ wr_ptr ] <= in_x;
else
buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ];
end
always @(posedge clk) begin
if( reset )
begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else
begin
if( !full && write )wr_ptr <= wr_ptr + 1;
else wr_ptr <= wr_ptr;
if( !emp && read ) rd_ptr <= rd_ptr + 1;
else rd_ptr <= rd_ptr;
end
end
endmodule
