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Altera_Forum
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15 years ago

Fixed Point Multiplication in Verilog or Quartus II

Hello, I plan to implement a controller digitally in my FPGA & it involves numerous fixed-point additions, multiplications & divisions. Therefore here is a generic question: Suppose ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

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Yes. Actually I was thinking of the case I3 = I2+I1, where no overflow occurs, except for the the product of the two most negative numbers. In case of I3 < I1 + I2, overflow has to be considered generally.

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I3=I2+I1

If no. of bit of I3 = I2+I1, it wont caused overflow. Let say -2*-2 = -4(mistake:is 4 actually). It is 100 in 2nd complement. How can it cause overflow since the I3 has 2+2= 4 bit?