Fixed Point Multiplication in Verilog or Quartus II

Yes. Actually I was thinking of the case I3 = I2+I1, where no overflow occurs, except for the the product of the two most negative numbers. In case of I3 < I1 + I2, overflow has to be considered generally.

In my opinion, saturation logic should be used to handle both cases. It can be implemented by comparing mult_32out[31] and mult_32out[30:P + 15] (following the above notation).

If any bit out of mult_32out[30:P + 15] is different from mult_32out[31], overflow has occured and the result has to be replaced by the most positive respectively most negative number.