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Altera_Forum
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15 years ago

Fixed Point Multiplication in Verilog or Quartus II

Hello, I plan to implement a controller digitally in my FPGA & it involves numerous fixed-point additions, multiplications & divisions. Therefore here is a generic question: Suppose ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

What FvM is talking about is the problems that happen when you multiply the two most negative numbers i.e.

A is 2 bits (1 sign bit + 1 bit)

B is 2 bits (1 sign bit + 1 bit)

Both A and B can represent decimal numbers between [-2 .. 1]

But if A=-2 and B=-2 then a overflow will occur and you need to take care of that.

FvM correct me if I'm wrong here.