Fixed Point Multiplication in Verilog or Quartus II

@amilcar : Thanks. The slicing idea seems nice !

@ FvM : Don't quite understand the problem you've suggested.

Right now, what I've done is the following:

As far as multiplication of fixed-point fractions is concerned, I've changed the product of fixed-point numbers A*B into the form:

a*b = k*l*(m/n)

where k & l = unknown integers; m & n are known integers.

(I've also chosen M & N such that N is a power of 2 (n = 2^p) , to replace the 'division-by-n' with 'p-lsbs cutoff' - since this will save time).

So now, I'm only concerned about integer multiplication.

For that I'm using the 'lpm_mult' megafunction in Quartus II. It generates (by default) a 32-bit result for two 16-bit signed input multiplicands. I store this result in mult_32out.

Now, i'm assuming that this "lpm_mult" computes its sign-bit correctly (i.e. deals with whatever problem you have specified).

So, then - I just take the mult_32out[31]-bit as the correct result sign bit, and proceed.

In the end, I have my required 16-bit result as:

result_axb = {mult_32out[31], mult_32out[p + 14 : p]};

Its simulation yields correct results, so my assumption seems to be correct. What say ?