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Altera_Forum
Honored Contributor
Honored ContributorFixed Point Multiplication in Verilog or Quartus II
Hello, I plan to implement a controller digitally in my FPGA & it involves numerous fixed-point additions, multiplications & divisions. Therefore here is a generic question: Suppose ...
Altera_ForumHonored Contributor
Honored ContributorIn signed multiply, you get two sign bits, not one. But you can't simply discard one of them, you need to handle the product of the two most negative numbers explicitely.
