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Altera_Forum
Honored Contributor
Honored ContributorFixed Point Multiplication in Verilog or Quartus II
Hello, I plan to implement a controller digitally in my FPGA & it involves numerous fixed-point additions, multiplications & divisions. Therefore here is a generic question: Suppose ...
Altera_ForumHonored Contributor
Honored ContributorI would say:
If A and B are signed, just multiply both (C<=A*B) and slice C correctly i.e. C[31] = sign C[30:18] = integer bits C[17:0] = fraction bits.
