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kanthi's avatar
kanthi
Icon for New Contributor rankNew Contributor
6 years ago

Fitter routing can't fit into device when we look the resource utilization is less than 60%. we are using stratix V device. how to fix this.

Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Altera Knowledge Database contains many articles with specific details on how to reso...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Bram will be running very slow, can you use M20k?

How do you use the ram? by calling out the IP or by coding?

If by using the IP, there should be an option for you to change it. If you are using coding, you can force it to use M20 using attribute.

Also, after you use M20k, make sure the register are tied inside the ram so that the performance will get better. You can check whether the register is pack to the ram in the syntheis/fitter reports.

kanthi's avatar
kanthi
Icon for New Contributor rankNew Contributor
6 years ago
Hi Mr.KTan How to fix this warning Warning (177007): PLL(s) placed in location FRACTIONALPLL_X98_Y11_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Info (177008): PLL mango_demo:mango_demo_0|mango_demo_bw_ddr3_system:bw_ddr3_system|mango_demo_bw_ddr3_system_bw_ddr3_mst:bw_ddr3_mst|mango_demo_bw_ddr3_system_bw_ddr3_mst_emif_0:emif_0|mango_demo_bw_ddr3_system_bw_ddr3_mst_emif_0_pll0:pll0|pll1~FRACTIONAL_PLL Warning (177007): PLL(s) placed in location FRACTIONALPLL_X98_Y109_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Info (177008): PLL mango_demo:mango_demo_0|mango_demo_bw_qdr2_system_0:bw_qdr2_system_0|mango_demo_bw_qdr2_system_0_qdra:qdra|mango_demo_bw_qdr2_system_0_qdra_qdr_0:qdr_0|mango_demo_bw_qdr2_system_0_qdra_qdr_0_pll0:pll0|pll1~FRACTIONAL_PLL Warning (177007): PLL(s) placed in location FRACTIONALPLL_X210_Y53_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks I set the value in assignment editior mango_demo:mango_demo_0|mango_demo_bw_qdr2_system_0:bw_qdr2_system_0|mango_demo_bw_qdr2_system_0_qdra:qdra|mango_demo_bw_qdr2_system_0_qdra_qdr_0:qdr_0|mango_demo_bw_qdr2_system_0_qdra_qdr_0_pll0:pll0|pll1~FRACTIONAL_PLL PLL compensate direct when i synthesis it was ignored thanks