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kanthi's avatar
kanthi
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6 years ago

Fitter routing can't fit into device when we look the resource utilization is less than 60%. we are using stratix V device. how to fix this.

Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Altera Knowledge Database contains many articles with specific details on how to reso...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

Bram will be running very slow, can you use M20k?

How do you use the ram? by calling out the IP or by coding?

If by using the IP, there should be an option for you to change it. If you are using coding, you can force it to use M20 using attribute.

Also, after you use M20k, make sure the register are tied inside the ram so that the performance will get better. You can check whether the register is pack to the ram in the syntheis/fitter reports.

kanthi's avatar
kanthi
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6 years ago
hi KTan, Thanks, we will try and let you know the result. here with i am enclosed our constraints file top.sdc -- please advice any changes or additional setup is require do you have any recommended setting for synthesis and fitting? when i do the design partition, some time the logic region is small in size (20% higher value we set from estimated size ). i adjusted the area then do the fitter (place and route). it is start from synthesis again. in general , we didn't change anything on the design level. already the synthesis and elaboration done. The Quartus tools start from the very beginning. it is taking more than for full compilation (more than 6 to 8 hr). is any other way to do only fitter(when i change only on design partition - "area size changes") so, we can save some time. thanks Mr. Ktan