Fitter routing can't fit into device when we look the resource utilization is less than 60%. we are using stratix V device. how to fix this.
Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Altera Knowledge Database contains many articles with specific details on how to reso...
Hi KTan,
Thank you very much for your guidance. Sorry for the delay update.
Now there is no slack factor on MM_interconnection
alternatively, the slack factor move in to other modules.
our utilization is less than 66% of resource. even though we are getting high slack factor
is any other way to remove this?
we can able to achieves if we disabled the BRAM (on chip memory).
is any alternate method for BRAM replacement
info:
Family Stratix V
Device 5SGXEA7K2F40C2
Timing Models Final
Logic utilization (in ALMs) N/A
Total registers 222223
Total pins 548
Total virtual pins 452
Total block memory bits 34,836,496
Total DSP Blocks 70
Total HSSI STD RX PCSs 9
Total HSSI 10G RX PCSs 2
Total HSSI GEN3 RX PCSs 9
Total HSSI PMA RX Deserializers 10
Total HSSI STD TX PCSs 9
Total HSSI 10G TX PCSs 2
Total HSSI GEN3 TX PCSs 9
Total HSSI PMA TX Serializers 11
Total HSSI PIPE GEN1_2s 9
Total HSSI GEN3s 9
Total PLLs 19
Total DLLs 2
Thanks KTan,
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