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Altera_Forum's avatar
Altera_Forum
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8 years ago

Fitter is assigning pins according to the old pin plan

Hi,

I have two FPGA designs for two different FPGAs(in Quartus).

I did one project for one FPGA and then then copied the same project and modified it according to second FPGA.

Now, I also changed the pin assignments in pin planner. But when I compiled the design, fitter is picking up pins according to both new and old i.e. the pins which are unassigned in new design are getting pin assignments from old design.

I tried to remove old Fitter assignments through Remove Assignments, but as soon as I re-compile design, old assignments appear in the pin planner.

I also deleted db and incremental_db. No use.

And if I download the same design on FPGA, my board my get burned.

So guys, what to do? I am running Quartus 16.1.2 Lite.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    You're saying that the assignments you've made in Pin Planner don't match what you see in the output .pin file after compilation? Very strange.

    Are you sure the new project is not still using the old project's .qsf file? How did you copy the project: in Explorer or Linux or did you use the Project Copy feature in Quartus?

    Can you try creating a new revision of the project (Project menu -> Revisions) and see if the adjusted assignments work when using a new revision?
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Same problem as with many posts, no readable attachments. Always review the attachments after posting.

    If I grasp right from the blurry image, there are no user assigned locations for most pins, looks like you didn't yet enter it. Without user assignments, the fitter selects arbitrary locations that most likely don't fit your needs.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Same problem as with many posts, no readable attachments. Always review the attachments after posting.

    If I grasp right from the blurry image, there are no user assigned locations for most pins, looks like you didn't yet enter it. Without user assignments, the fitter selects arbitrary locations that most likely don't fit your needs.

    --- Quote End ---

    Thank you for reply.

    I actually have assigned three pins for my design. I don't need more than this. But again, the fitter is picking many other pins, which I certainly do not require.

    So any idea why?
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Are the signals listed there top-level ports in your design? If so, the Fitter is going to assign them to I/O pins unless you add virtual pin assignments.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Are the signals listed there top-level ports in your design? If so, the Fitter is going to assign them to I/O pins unless you add virtual pin assignments.

    --- Quote End ---

    Actually sir, there are only two pins in my top level module. Rest of the pins are not in my new (modified) design. The pins which are showing up now, were in my previous design, from which I copied my current design(I copied whole of the project folder).
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    The signals exist somewhere. Open up the project's .qsf file and remove any old assignments you see there.

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    The signals exist somewhere. Open up the project's .qsf file and remove any old assignments you see there.

    --- Quote End ---

    Yes, you are right. The entries were in qsf file.

    Thank you sir.