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Altera_Forum
Honored Contributor
9 years agoFitter can't place 1 fractional PLL
Hi, we have a Cyclone V SX design that fails to compile because the fitter can't place 1 fractional PLL. I have compiled the design succesfully previously, but after I added two 2-lane HiSPi...
Altera_Forum
Honored Contributor
9 years agoHi Joonas,
maybe you use just one LVDS_RX block with two channels or the "Use External PLL" option to share one PLL between the LVDS_RXs and other clocks. regards Jens