Altera_ForumHonored Contributor13 years agoFitter Added Delay and False Paths Hi All, I have a design with a bank of configuration registers, that run to various state machines with different gated or muxed clocks. The reigster outputs are quasi-static, so I don't want ...Show More
Altera_ForumHonored Contributor13 years agoAre you sure the fiter is not adding delay to the *input* of those registers?
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