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Altera_Forum's avatar
Altera_Forum
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12 years ago

First VHDL try

Hi to all

I'm trying my first VHDL code to replace a GAL

Quartus tells me :

Warning (10325): VHDL Choice warning at gal.vhd(30): ignored choice containing meta-value ""01XXXXXXXX00XXXX""

Warning (10325): VHDL Choice warning at gal.vhd(31): ignored choice containing meta-value ""01111111XX10XXXX""

Warning (10325): VHDL Choice warning at gal.vhd(32): ignored choice containing meta-value ""010XXXXXXX10XXXX""

Warning (10325): VHDL Choice warning at gal.vhd(33): ignored choice containing meta-value ""0110XXXXXX10XXXX""

Warning (10325): VHDL Choice warning at gal.vhd(34): ignored choice containing meta-value ""01110XXXXX10XXXX""

Warning (10325): VHDL Choice warning at gal.vhd(35): ignored choice containing meta-value ""011110XXXX10XXXX""

Warning (10325): VHDL Choice warning at gal.vhd(36): ignored choice containing meta-value ""0111110X0X10XXX0""

Warning (10325): VHDL Choice warning at gal.vhd(37): ignored choice containing meta-value ""0111110X0X10XXX1""

Warning (10325): VHDL Choice warning at gal.vhd(38): ignored choice containing meta-value ""0111110XX010XXX0""

Warning (10325): VHDL Choice warning at gal.vhd(39): ignored choice containing meta-value ""0111110X1X10XXX1""

Warning (10325): VHDL Choice warning at gal.vhd(40): ignored choice containing meta-value ""0111110XX010XXX1""

Warning (10325): VHDL Choice warning at gal.vhd(41): ignored choice containing meta-value ""011111100X10XXXX""

Warning (10325): VHDL Choice warning at gal.vhd(42): ignored choice containing meta-value ""011111101X10XXXX""

Warning (10325): VHDL Choice warning at gal.vhd(43): ignored choice containing meta-value ""01111110X010XXXX""

Warning (10873): Using initial value X (don't care) for net "dq" at gal.vhd(15)

:(

This is my code :

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.ALL;

ENTITY GAL IS

PORT (

a : IN std_logic_vector(15 downto 0);

dq : OUT std_logic_vector(8 downto 1)

);

END GAL;

-- =============================================================================

-- =============================================================================

ARCHITECTURE bus_decode OF GAL IS

-- =============================================================================

BEGIN

PROCESS(a(15 downto 0))

BEGIN

CASE a(15 downto 0) IS

when "0100000110X00100" => dq(8 downto 1) <= "10111111";

when "01XXXXXXXX00XXXX" => dq(8 downto 1) <= "01111111";

when "01111111XX10XXXX" => dq(8 downto 1) <= "01111111";

when "010XXXXXXX10XXXX" => dq(8 downto 1) <= "01111111";

when "0110XXXXXX10XXXX" => dq(8 downto 1) <= "01111111";

when "01110XXXXX10XXXX" => dq(8 downto 1) <= "01111111";

when "011110XXXX10XXXX" => dq(8 downto 1) <= "01111111";

when "0111110X0X10XXX0" => dq(8 downto 1) <= "11011001";

when "0111110X0X10XXX1" => dq(8 downto 1) <= "11110111";

when "0111110XX010XXX0" => dq(8 downto 1) <= "11011111";

when "0111110X1X10XXX1" => dq(8 downto 1) <= "11101111";

when "0111110XX010XXX1" => dq(8 downto 1) <= "11101110";

when "011111100X10XXXX" => dq(8 downto 1) <= "11111001";

when "011111101X10XXXX" => dq(8 downto 1) <= "11001111";

when "01111110X010XXXX" => dq(8 downto 1) <= "11001110";

END CASE;

END PROCESS;

Can anyone help please ?

23 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    in VHDL 'X' means Unknown, not dont care, dont care is '-'

    But VHDL also has strong typing, so comparing an input of 4 bits to "1XXX" will look for that string literally during simulation, so "1000 will NOT match, only "1XXX" will match.

    To do what you are doing, you need to use the matching case statement from VHDL 2008 (case?), that will try and match dont cares: 

    
case? a is
  when "0100000110-00100" => dq(8 downto 1) <= "10111111"; 
  when "01--------00----" => dq(8 downto 1) <= "01111111";
--etc

    otherwise, if you're stuck with VHDL 93, you can use the std_match function from the std_logic_misc library 

    
if std_match(a, "01000000110-00100") then
---
elsif std_match(a, "01--------00----") then
--etc

    This way simulation will match your hardware.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    It doesn't work in my project because this error:

    Warning (10873): Using initial value X (don't care) for net "dq" at gal.vhd(15)

    Using CASE or IF
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    My code :

    if std_match(a, "0100000110-00100") then dq <= "10111111";

    elsif std_match(a, "01--------00----") then dq <= "01111111";

    end if;

    Error :

    Error (10482): VHDL error at gal.vhd(29): object "std_match" is used but not declared
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi fabf.

    The don't care '-' and 'X' are non synthesizable metavalues so don't use it. You can't use it like Karnaugh map o true table don't care. To replace it you have assigment sentences with priority, like when o if-elsif-else. I'll use if. For example you have:

    when "01XXXXXXXX00XXXX" => dq(8 downto 1) <= "01111111";

    You can code it:

    process...

    begin

    if( a(15 downto 14) = "01" and a(5 downto 4) = "00" ) then

    dq(8 downto 1) <= "01111111";

    elsif( .....

    The first if only use bits 4, 5, 14, 15. Don't look other bits. So they don't care, and the other if are not evaluated. This way you can write a synthesizable code with don't care. You have to unroll the original true table with the don't cares and translate into vhdl.