First VHDL try

Hi fabf.

The don't care '-' and 'X' are non synthesizable metavalues so don't use it. You can't use it like Karnaugh map o true table don't care. To replace it you have assigment sentences with priority, like when o if-elsif-else. I'll use if. For example you have:

when "01XXXXXXXX00XXXX" => dq(8 downto 1) <= "01111111";

You can code it:

process...

begin

if( a(15 downto 14) = "01" and a(5 downto 4) = "00" ) then

dq(8 downto 1) <= "01111111";

elsif( .....

The first if only use bits 4, 5, 14, 15. Don't look other bits. So they don't care, and the other if are not evaluated. This way you can write a synthesizable code with don't care. You have to unroll the original true table with the don't cares and translate into vhdl.