fir filter code in vhdl [plzzzzzz reply as fast as possible plzzzz]

I had a quick look at your code. It looks ok to me in principle.

To test better check your method and use this:

y = filter([h0 h1 h2 h3],1,x);

Also check fmax. You have long paths through mult then add

Here are some further notes:

Your code is certainly correct and readable (But be careful,I did not simulate it).

Regarding fmax, if I assume your FIR is the full project inside an FPGA then you donot have registers at inputs or output and so timing will not find any paths to report.

i.e. your design is fully combinatorial and may fail due to variable delay so add registers at inputs/outputs and mult results.

Another note: you have inferred mult and add and that is ok but you have not inferred registers between adders in your transpose pipe. It looks a bit unbalanced in that you can equally infer them on the clock edge.

Finally your fir is certainly intuitive but don't know what 4 such taps will do in practice. An example application might be digital amplitude predistortion but that is too involved and requires coeff updating.

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Here are some further notes:

Your code is certainly correct and readable (But be careful,I did not simulate it).

Regarding fmax, if I assume your FIR is the full project inside an FPGA then you donot have registers at inputs or output and so timing will not find any paths to report.

i.e. your design is fully combinatorial and may fail due to variable delay so add registers at inputs/outputs and mult results.

Another note: you have inferred mult and add and that is ok but you have not inferred registers between adders in your transpose pipe. It looks a bit unbalanced in that you can equally infer them on the clock edge.

Finally your fir is certainly intuitive but don't know what 4 such taps will do in practice. An example application might be digital amplitude predistortion but that is too involved and requires coeff updating.

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hello,

thnx for the reply...this is my basic project work and here im supposed to just simulate it and show the correct o/p which matches with the fir formula.

i have put registers to add,mux ..still not working ....help plzzz.

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and where is the testbench?

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i dont use any test bench .As a begginer my guide advised me to use vhdl test bench (by default present in xilinx)

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hello,

thnx for the reply...this is my basic project work and here im supposed to just simulate it and show the correct o/p which matches with the fir formula.

i have put registers to add,mux ..still not working ....help plzzz.

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plzz reply me as fast as possible plzzzz im in urgent need of this

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If you are only simulating(functional) then don't worry about adding registers. In all cases don't put any registers between adders as this will affect fir function. I advise you go back to first code. It is ok, you are not testing correctly. Show me few samples of your input and output.

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thnx for the reply and cooperation sir

my h=[-2 -1 3 4]

im giving inputs x=[0 -3 1 0 ]

i shud get y=[0 6 1 -10 ]

according to fir formula y0=x0h0, y1=x0h1+x1h0, y2=x0h2+x1h1+x2h0 , y3=x0h3+x1h2+x2h1+x3h0

but when i simulate my code im getting y=[0 6 0 4] y0,y1 are correct.

plzz reply me fast sir.......

yes you should get [0 6 1 -10]

Are you inputting x correctly just after clock edge. can you post how you drive x?