fir filter code in vhdl [plzzzzzz reply as fast as possible plzzzz]

Here are some further notes:

Your code is certainly correct and readable (But be careful,I did not simulate it).

Regarding fmax, if I assume your FIR is the full project inside an FPGA then you donot have registers at inputs or output and so timing will not find any paths to report.

i.e. your design is fully combinatorial and may fail due to variable delay so add registers at inputs/outputs and mult results.

Another note: you have inferred mult and add and that is ok but you have not inferred registers between adders in your transpose pipe. It looks a bit unbalanced in that you can equally infer them on the clock edge.

Finally your fir is certainly intuitive but don't know what 4 such taps will do in practice. An example application might be digital amplitude predistortion but that is too involved and requires coeff updating.