Finite State Machine..

Hello,

i have problem here..

please help me out..

I'm designing a vending machine that accept only coins( 10 cent, 20 cent, and 50 cent)

A = 10 cent

B = 20 cent

C = 50 cent

the error still appear after simulation even i edit the coding several times.

:(

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY fsm1 is

PORT ( clk, rst : in std_logic;

A, B, C : in std_logic;

Z : out std_logic);

END fsm1;

ARCHITECTURE structural of fsm1 is

TYPE state is ( s0, s1, s2, s3, s4, s5, s6, s7 );

SIGNAL y : state;

BEGIN

fsm_transition: PROCESS ( clk, rst)

BEGIN

IF rst = '1' THEN y <= s0;

ELSIF clk'event and clk = '1' THEN

CASE y is

WHEN s0 => IF A = '1' THEN y <= s1;

ELSIF B = '1' THEN y <= s2;

ELSIF C = '1' THEN y <= s5;

ELSE y <= s0;

END IF;

WHEN s1 => IF A = '1' THEN y <= s2;

ELSIF B = '1' THEN y <= s3;

ELSIF C = '1' THEN y <= s6;

ELSE y <= s1;

END IF;

WHEN s2 => IF A = '1' THEN y <= s3;

ELSIF B = '1' THEN y <= s4;

ELSIF C = '1' THEN y <= s7;

ELSE y <= s2;

END IF;

WHEN s3 => IF A = '1' THEN y <= s4;

ELSIF B = '1' THEN y <= s5;

ELSIF C = '1' THEN y <=s7;

ELSE y <= s3;

END IF;

WHEN s4 => IF A = '1' THEN y <= s5;

ELSIF B = '1' THEN y <= s6;

ELSIF C = '1' THEN y <= s7;

ELSE y <= s4;

END IF;

WHEN s5 => IF A = '1' THEN y <= s6;

ELSIF B = '1' THEN y <= s7;

ELSIF C = '1' THEN y <= s7;

ELSE y <= s5;

END IF;

WHEN s6 => IF A = '1' THEN y <= s7;

ELSIF B = '1' THEN y <= s7;

ELSIF C = '1' THEN y <= s7;

ELSE y <= s6;

END IF;

END CASE;

END IF;

END PROCESS fsm_transition;

Z <= '1' WHEN y = s7 ELSE '0';

END structural;