Finding FPGA designers and best practices for Quartus projects under Git?

Hi,

Check this link https://community.intel.com/t5/Intel-Quartus-Prime-Software/Version-control-for-the-Quartus-project/m-p/130387

Basically following files are required under version control:

• .qpf
• .qsf
• .qsys ( Helps to regenerate your QSYS design. )
• .sopcinfo ( required by software team )
• .sof
• Verilog files designed by you ( Files generated by QSYS don't seem to be required there on repository as they will be generated each time you regenerate your Qsys system. So you may not wish to upload synthesis folder on repository. )
• Verilog files generated by Megawizard plug in manager.( As it will contain information about customization of particular mega function. )
• .pin file ( Contains information about all pins in your design. Although it can be eliminated, it may be useful. )
• .sdc file which you have prepared.( SDC files auto generated by Quartus may be ignored. )

Probably have to save the .qsys file and all the individual .ip files used in the project. This has been made easy by archiving the whole Platform Designer into a single .zip or .tcl file, here are some guidance:

https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/saving-systems.html

https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/archiving-systems.html

https://www.intel.com/content/www/us/en/docs/programmable/683609/22-4/including-systems-in-project-archives.html

Check this link https://community.intel.com/t5/Programmable-Devices/Prime-Pro-Edition-Source-files-meaning-of-folder-quot-tmp/m-p/205082

As far as revision control, using the project archiving feature is the easiest way to manage it to make sure all files get included.

Regards,

Sheng