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I already recommended you use numeric_std for the signed/unsigned types. Using std_logic_vector is just messy, and there is no need to use the LPM library. why are you insisting on this?
Secondly - your attempt to use shared variables shows lack of understanding of VHDL, and given your postings here and elsewhere, I suspect your knowledge of digital logic could also use some revision.
I also recommend you try using modelsim as well.
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I'm sorry.. i'm only a student of vhdl.. i started use vhdl two mouths ago, so i read only some notes. but i must use vhdl.:(
if you help me i can improve my knowledge. thanks.
Honored Contributor
